Over time, semiconductors are fabricated in smaller-and-smaller sizes. Random Access Memory circuits often leading the forefront in the continuing shrinking-size race.
From 90 nanometers (nm) and beyond, the thin style memory cell structure has been became a key structure for high density embedded Static Random Access Memory (SRAM). As shown in FIG. 1, a SRAM chip 1000 has a dual-port (DP) unit cell array 1100 boarded by row-edge dummy cells 1200a-b, and two word lines 1300a-b. The unit cell array contains SRAM cells organized in rows-and-columns. In such cells, the length ratio of bit-line/word-line is less than 1/2 in single-port memory, or 1/3 in dual-port (“two-port”) memory. These kind of cells have lower bit-line/word-line conductor length ratio in a unit cell for an index of lower bit-line loading effect for high speed application. On the other hand, these thin style cells also result in higher word line coupling capacitance due to longer word-line and narrow spacing. This induces worse word-line coupling noise between adjacent word-lines (like Dual-port's word-line-A to word-line-B, or adjacent bit's word-line).
To have smaller cell sizes, the cell height (in the bit-line routing direction) design is usually pushed to two gate-pitches dimension, and therefore allowed only 2 metal-word-lines routing in one cell. This means two adjacent word-lines have no additional metal line (such as Vss or Vdd) for noise shielding purposes. From cell stability point of view (word-line to word-line noise coupling), this worse word-line coupling noise will become a barrier to decreasing cell size.